Issued Patents 2024
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183424 | Bit-cell architecture based in-memory compute | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori +2 more | 2024-12-17 |
| 12118451 | Deep convolutional network heterogeneous architecture | Giuseppe Desoli, Thomas Boesch, Surinder Singh, Elio Guidetti, Fabio Giuseppe DE AMBROGGI +2 more | 2024-10-15 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-09-10 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-05-14 |
| 11900240 | Variable clock adaptation in neural network processors | Giuseppe Desoli, Manuj AYODHYAWASI, Thomas Boesch, Surinder Singh | 2024-02-13 |