Issued Patents 2024
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183424 | Bit-cell architecture based in-memory compute | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Manuj AYODHYAWASI +2 more | 2024-12-17 |
| 12165698 | Circuitry for adjusting retention voltage of a static random access memory (SRAM) | — | 2024-12-10 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-09-10 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2024-05-14 |