Issued Patents 2023
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853424 | Processor that mitigates side channel attacks by refraining from allocating an entry in a data TLB for a missing load address when the load address misses both in a data cache memory and in the data TLB and the load address specifies a location without a valid address translation or without permission to read from the location | Srivatsan Srinivasan | 2023-12-26 |
| 11841802 | Microprocessor that prevents same address load-load ordering violations | Srivatsan Srinivasan | 2023-12-12 |
| 11836498 | Single cycle predictor | Michael N. Michael | 2023-12-05 |
| 11836080 | Physical address proxy (PAP) residency determination for reduction of PAP reuse | Srivatsan Srinivasan, Robert Haskell Utley | 2023-12-05 |
| 11822487 | Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer | George Van Horn Leming, III, Stephan Jourdan, Jonathan Christopher Perry, Bret L. Toll | 2023-11-21 |
| 11816489 | Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one per clock cycle | Michael N. Michael | 2023-11-14 |
| 11803637 | Microprocessor that prevents store-to-load forwarding between different translation contexts | — | 2023-10-31 |
| 11803638 | Microprocessor core with a store dependence predictor accessed using a translation context | — | 2023-10-31 |
| 11797673 | Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception | Srivatsan Srinivasan | 2023-10-24 |
| 11755731 | Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks | David S. Oliver | 2023-09-12 |
| 11755732 | Microprocessor that conditions store-to-load forwarding on circumstances associated with a translation context update | — | 2023-09-12 |
| 11734426 | Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location | Srivatsan Srinivasan | 2023-08-22 |
| 11733972 | Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address | Srivatsan Srinivasan | 2023-08-22 |
| 11687466 | Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions | Srivatsan Srinivasan | 2023-06-27 |
| 11625479 | Virtually-tagged data cache memory that uses translation context to make entries allocated during execution under one translation context inaccessible during execution under another translation context | Srivatsan Srinivasan | 2023-04-11 |
| 11620377 | Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context | Srivatsan Srinivasan | 2023-04-04 |