Issued Patents 2023
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853424 | Processor that mitigates side channel attacks by refraining from allocating an entry in a data TLB for a missing load address when the load address misses both in a data cache memory and in the data TLB and the load address specifies a location without a valid address translation or without permission to read from the location | John G. Favor | 2023-12-26 |
| 11841802 | Microprocessor that prevents same address load-load ordering violations | John G. Favor | 2023-12-12 |
| 11836080 | Physical address proxy (PAP) residency determination for reduction of PAP reuse | John G. Favor, Robert Haskell Utley | 2023-12-05 |
| 11797673 | Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception | John G. Favor | 2023-10-24 |
| 11734426 | Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location | John G. Favor | 2023-08-22 |
| 11733972 | Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address | John G. Favor | 2023-08-22 |
| 11687466 | Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions | John G. Favor | 2023-06-27 |
| 11625479 | Virtually-tagged data cache memory that uses translation context to make entries allocated during execution under one translation context inaccessible during execution under another translation context | John G. Favor | 2023-04-11 |
| 11620377 | Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context | John G. Favor | 2023-04-04 |