BT

Bret L. Toll

IN Intel: 18 patents #62 of 4,378Top 2%
AC Ampere Computing: 2 patents #1 of 9Top 15%
Overall (2023): #2,061 of 537,848Top 1%
20
Patents 2023

Issued Patents 2023

Patent #TitleCo-InventorsDate
11847452 Systems, methods, and apparatus for tile configuration Menachem Adelman, Robert Valentine, Zeev Sperber, Mark J. Charney, Rinat Rappoport +6 more 2023-12-19
11822487 Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer George Van Horn Leming, III, John G. Favor, Stephan Jourdan, Jonathan Christopher Perry 2023-11-21
11816483 Systems, methods, and apparatuses for matrix operations Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2023-11-14
11809869 Systems and methods to store a tile register pair to memory Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2023-11-07
11789729 Systems and methods for computing dot products of nibbles in two tile operands Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +4 more 2023-10-17
11748103 Systems and methods for performing matrix compress and decompress instructions Dan Baum, Michael Espig, James D. Guilford, Wajdi K. Feghali, Raanan Sade +7 more 2023-09-05
11748130 Virtualization and multi-tenancy support in graphics processors Rajesh M. Sankaran, William C. Rash, Subramaniam Maiyuran, Gang Chen, Varghese George 2023-09-05
11740904 Vector friendly instruction format and execution thereof Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Santiago Galan Duran +14 more 2023-08-29
11714642 Systems, methods, and apparatuses for tile store Robert Valentine, Menachem Adelman, Elmoustapha Ould-Ahmed-Vall, Milind B. Girkar, Zeev Sperber +9 more 2023-08-01
11714648 Systems for performing instructions to quickly convert and use tiles as 1D vectors Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Raanan Sade, Robert Valentine +2 more 2023-08-01
11709961 Instruction execution that broadcasts and masks data values at different levels of granularity Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Mark J. Charney 2023-07-25
11675590 Systems and methods for performing instructions to transform matrices into row-interleaved format Raanan Sade, Robert Valentine, Christopher J. Hughes, Alexander Heinecke, Elmoustapha Ould-Ahmed-Vall +1 more 2023-06-13
11669326 Systems, methods, and apparatuses for dot product operations Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2023-06-06
11645077 Systems and methods to zero a tile register pair Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +6 more 2023-05-09
11609762 Systems and methods to load a tile register pair Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2023-03-21
11586537 Method, apparatus, and system for run-time checking of memory tags in a processor-based system Benjamin Crawford Chaffin, Jonathan Christopher Perry, Nagi Aboulenein 2023-02-21
11579883 Systems and methods for performing horizontal tile operations Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Raanan Sade, Robert Valentine +2 more 2023-02-14
11579880 Systems for performing instructions to quickly convert and use tiles as 1D vectors Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Raanan Sade, Robert Valentine +2 more 2023-02-14
11579871 Systems, apparatuses, and methods for controllable sine and/or cosine operations Venkateswara Madduri, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Mark J. Charney +2 more 2023-02-14
11567765 Systems, methods, and apparatuses for tile load Robert Valentine, Menachem Adelman, Milind B. Girkar, Zeev Sperber, Mark J. Charney +9 more 2023-01-31