Issued Patents 2023
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11816032 | Cache size change | Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan | 2023-11-14 |
| 11803486 | Write merging on stores with different privilege levels | Timothy David Anderson, Pete Michael Hippleheuser | 2023-10-31 |
| 11803382 | Look-up table read | Duc Quang Bui, Dheera Balasubramanian Samudrala, Rama Venkatasubramanian | 2023-10-31 |
| 11789868 | Hardware coherence signaling protocol | Abhijeet Ashok Chachad, David Matthew Thompson, Pete Michael Hippleheuser | 2023-10-17 |
| 11782718 | Implied fence on stream open | Kai Chirca, Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2023-10-10 |
| 11775302 | Histogram operation | Duc Quang Bui, Rama Venkatasubramanian, Dheera Balasubramanian Samudrala, Alan L. Davis | 2023-10-03 |
| 11775446 | Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2023-10-03 |
| 11762780 | Write merging on stores with different tags | Timothy David Anderson, Pete Michael Hippleheuser | 2023-09-19 |
| 11740930 | Global coherence operations | Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan | 2023-08-29 |
| 11741020 | Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding | Timothy David Anderson, Pete Michael Hippleheuser | 2023-08-29 |
| 11720495 | Multi-level cache security | Abhijeet Ashok Chachad, David Matthew Thompson | 2023-08-08 |
| 11714760 | Methods and apparatus to reduce bank pressure using aggressive write merging | Timothy David Anderson, Pete Michael Hippleheuser | 2023-08-01 |
| 11714754 | Shadow caches for level 2 cache controller | Abhijeet Ashok Chachad, David Matthew Thompson | 2023-08-01 |
| 11709677 | Look-up table initialize | Dheera Balasubramanian Samudrala, Duc Quang Bui, Rama Venkatasubramanian | 2023-07-25 |
| 11693791 | Victim cache that supports draining write-miss entries | Timothy David Anderson, Pete Michael Hippleheuser | 2023-07-04 |
| 11693790 | Methods and apparatus to facilitate write miss caching in cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2023-07-04 |
| 11687457 | Hardware coherence for memory controller | Abhijeet Ashok Chachad, David Matthew Thompson | 2023-06-27 |
| 11640357 | Methods and apparatus to facilitate read-modify-write support in a victim cache | Timothy David Anderson, Pete Michael Hippleheuser | 2023-05-02 |
| 11636040 | Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue | Timothy David Anderson, Pete Michael Hippleheuser | 2023-04-25 |
| 11620230 | Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths | Timothy David Anderson, Pete Michael Hippleheuser | 2023-04-04 |