| 11816032 |
Cache size change |
Abhijeet Ashok Chachad, Naveen Bhoria, Neelima Muralidharan |
2023-11-14 |
| 11803505 |
Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels |
Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson |
2023-10-31 |
| 11789868 |
Hardware coherence signaling protocol |
Abhijeet Ashok Chachad, Naveen Bhoria, Pete Michael Hippleheuser |
2023-10-17 |
| 11768733 |
Error correcting codes for multi-master memory controller |
Abhijeet Ashok Chachad, Son Hung Tran |
2023-09-26 |
| 11762683 |
Merging data for write allocate |
Abhijeet Ashok Chachad |
2023-09-19 |
| 11740930 |
Global coherence operations |
Abhijeet Ashok Chachad, Naveen Bhoria, Neelima Muralidharan |
2023-08-29 |
| 11720495 |
Multi-level cache security |
Abhijeet Ashok Chachad, Naveen Bhoria |
2023-08-08 |
| 11714754 |
Shadow caches for level 2 cache controller |
Abhijeet Ashok Chachad, Naveen Bhoria |
2023-08-01 |
| 11687457 |
Hardware coherence for memory controller |
Abhijeet Ashok Chachad, Naveen Bhoria |
2023-06-27 |
| 11675700 |
Cache coherence shared state suppression |
Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca |
2023-06-13 |
| 11675660 |
Parallelized scrubbing transactions |
Abhijeet Ashok Chachad |
2023-06-13 |
| 11620236 |
Prefetch kill and revival in an instruction cache |
Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong |
2023-04-04 |
| 11609818 |
Pipelined read-modify-write operations in cache memory |
Abhijeet Ashok Chachad, Daniel Wu |
2023-03-21 |
| 11580024 |
Memory pipeline control in a hierarchical memory system |
Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca |
2023-02-14 |
| 11567874 |
Prefetch management in a hierarchical cache system |
Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong |
2023-01-31 |