Issued Patents 2023
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853225 | Software-hardware memory management modes | Joseph Zbiciak, Kai Chirca, Daniel Wu | 2023-12-26 |
| 11836494 | System and method for addressing data in memory | Duc Quang Bui, Joseph Zbiciak, Kai Chirca | 2023-12-05 |
| 11829300 | Method and apparatus for vector sorting using vector permutation logic | Mujibur Rahman | 2023-11-28 |
| 11822786 | Delayed snoop for improved multi-process false sharing parallel thread performance | Kai Chirca | 2023-11-21 |
| 11816485 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2023-11-14 |
| 11803486 | Write merging on stores with different privilege levels | Naveen Bhoria, Pete Michael Hippleheuser | 2023-10-31 |
| 11804858 | Butterfly network on load data return | Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui | 2023-10-31 |
| 11803505 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2023-10-31 |
| 11789742 | Pipeline protection for CPUs with save and restore of intermediate results | Duc Quang Bui, Joseph Zbiciak, Reid E. Tatge | 2023-10-17 |
| 11782718 | Implied fence on stream open | Naveen Bhoria, Kai Chirca, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2023-10-10 |
| 11775446 | Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2023-10-03 |
| 11768685 | Processing device with vector transformation execution | Mujibur Rahman, Joseph Zbiciak | 2023-09-26 |
| 11762780 | Write merging on stores with different tags | Naveen Bhoria, Pete Michael Hippleheuser | 2023-09-19 |
| 11755203 | Multicore shared cache operation engine | Kai Chirca, Matthew D. Pierson, David E. Smith | 2023-09-12 |
| 11755322 | Vector load and duplicate operations | Duc Quang Bui, Peter Richard Dent | 2023-09-12 |
| 11741020 | Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding | Naveen Bhoria, Pete Michael Hippleheuser | 2023-08-29 |
| 11734194 | Method and apparatus for dual issue multiply instructions | Mujibur Rahman | 2023-08-22 |
| 11714760 | Methods and apparatus to reduce bank pressure using aggressive write merging | Naveen Bhoria, Pete Michael Hippleheuser | 2023-08-01 |
| 11709778 | Streaming engine with early and late address and loop count registers to track architectural state | Joseph Zbiciak | 2023-07-25 |
| 11704046 | Quick clearing of registers | Duc Quang Bui, Soujanya Narnur | 2023-07-18 |
| 11693791 | Victim cache that supports draining write-miss entries | Naveen Bhoria, Pete Michael Hippleheuser | 2023-07-04 |
| 11693790 | Methods and apparatus to facilitate write miss caching in cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2023-07-04 |
| 11693661 | Mechanism for interrupting and resuming execution on an unprotected pipeline processor | Joseph Zbiciak, Kai Chirca | 2023-07-04 |
| 11681526 | Method and apparatus for vector based finite impulse response (FIR) filtering | Mujibur Rahman, Asheesh Bhardwaj | 2023-06-20 |
| 11681532 | Method for forming constant extensions in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2023-06-20 |