Issued Patents 2023
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11856865 | Gradient protection layer in MTJ manufacturing | Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien-Chung Huang +2 more | 2023-12-26 |
| 11854820 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2023-12-26 |
| 11854766 | DC bias in plasma process | Sheng-Liang Pan, Bing Chen, Chia-Yang Hung, Shu-Huei Suen, Syun-Ming Jang +1 more | 2023-12-26 |
| 11796922 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Shu-Huei Suen +7 more | 2023-10-24 |
| 11800812 | Integrated circuit | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2023-10-24 |
| 11784056 | Self-aligned double patterning | Kuan-Wei Huang, Yu-Yu Chen | 2023-10-10 |
| 11735469 | Method of forming a semiconductor device | Yi-Nien Su, Shu-Huei Suen, Ru-Gun Liu | 2023-08-22 |
| 11710657 | Middle-of-line interconnect structure having air gap and method of fabrication thereof | Yi-Nien Su | 2023-07-25 |
| 11683991 | Semiconductor structure and manufacturing method of the same | Tai-Yen Peng, Yu-Shu Chen, Chien-Chung Huang, Sin-Yi Yang, Chen-Jung Wang +2 more | 2023-06-20 |
| 11676821 | Self-aligned double patterning | Kuan-Wei Huang, Yu-Yu Chen | 2023-06-13 |
| 11665971 | Metal etching stop layer in magnetic tunnel junction memory cells | Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien-Chung Huang +2 more | 2023-05-30 |
| 11588107 | Integrated circuit structure | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2023-02-21 |