| 11830818 |
Semiconductor device having metal interconnects with different thicknesses |
Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi |
2023-11-28 |
| 11824002 |
Variable pitch and stack height for high performance interconnects |
En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Jiansheng Xu |
2023-11-21 |
| 11823954 |
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu |
2023-11-21 |
| 11764260 |
Dielectric and isolation lower fin material for fin-based electronics |
Walid M. Hafez |
2023-09-19 |
| 11737362 |
Harvesting energy in an integrated circuit using the seebeck effect |
Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi |
2023-08-22 |
| 11695008 |
Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process |
Curtis Tsai, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez |
2023-07-04 |
| 11688792 |
Dual self-aligned gate endcap (SAGE) architectures |
Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao +2 more |
2023-06-27 |
| 11610917 |
High voltage three-dimensional devices having dielectric liners |
Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti |
2023-03-21 |
| 11605632 |
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls |
Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Nick Lindert +2 more |
2023-03-14 |
| 11562999 |
Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture |
Roman W. Olac-Vaw, Nick Lindert, Walid M. Hafez |
2023-01-24 |
| 11563000 |
Gate endcap architectures having relatively short vertical stack |
Sairam Subramanian, Walid M. Hafez, Hsu-Yu Chang |
2023-01-24 |