Issued Patents 2022
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11515417 | Transistors including heterogeneous channels | Scott E. Sills, Ramanathan Gandhi, Yi Fang Lee, Kamal M. Karda | 2022-11-29 |
| 11501817 | Memory cell imprint avoidance | Alessandro Calderoni, Kirk D. Prall, Ferdinando Bedeschi | 2022-11-15 |
| 11476262 | Methods of forming an array of capacitors | Fatma Arzum Simsek-Ege | 2022-10-18 |
| 11476259 | Memory devices including void spaces between transistor features, and related semiconductor devices and electronic systems | Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Sanh D. Tang +1 more | 2022-10-18 |
| 11476252 | Memory device having 2-transistor vertical memory cell and shared channel region | Karthik Sarpatwari, Kamal M. Karda, Haitao Liu | 2022-10-18 |
| 11437521 | Methods of forming a semiconductor device | Scott E. Sills, Ramanathan Gandhi | 2022-09-06 |
| 11417381 | Memory device having shared read/write access line for 2-transistor vertical memory cell | Karthik Sarpatwari, Kamal M. Karda | 2022-08-16 |
| 11411002 | Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array | — | 2022-08-09 |
| 11404217 | Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker devices | Ashonita A. Chavan, Beth R. Cook, Manuj Nahar | 2022-08-02 |
| 11398571 | Devices and electronic systems including vertical transistors, and related methods | Scott E. Sills | 2022-07-26 |
| 11393978 | Array of cross point memory cells | Scott E. Sills, Alessandro Calderoni | 2022-07-19 |
| 11367730 | Cell disturb prevention using a leaker device to reduce excess charge from an electronic device | — | 2022-06-21 |
| 11348932 | Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies | Kamal M. Karda, Haitao Liu, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey | 2022-05-31 |
| 11335788 | Semiconductor devices, transistors, and related methods for contacting metal oxide semiconductor devices | Ramanathan Gandhi, Scott E. Sills | 2022-05-17 |
| 11335684 | Memory device having 2-transistor memory cell and access line plate | Kamal M. Karda, Karthik Sarpatwari, Haitao Liu | 2022-05-17 |
| 11315939 | Methods of incorporating leaker-devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker-devices | Alessandro Calderoni, Beth R. Cook, Ashonita A. Chavan | 2022-04-26 |
| 11296094 | Memory device having shared access line for 2-transistor vertical memory cell | Kamal M. Karda, Karthik Sarpatwari, Haitao Liu | 2022-04-05 |
| 11276449 | Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays | Wayne Kinney | 2022-03-15 |
| 11257838 | Thickened sidewall dielectric for memory cell | Ronald A. Weimer, Kyu S. Min, Thomas M. Graettinger | 2022-02-22 |
| 11244951 | Memory cells | Kamal M. Karda, Qian Tao, Haitao Liu, Kirk D. Prall, Ashonita A. Chavan | 2022-02-08 |
| 11244952 | Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells | Sameer Chhajed, Ashonita A. Chavan, Mark Fischer | 2022-02-08 |
| 11222690 | Vertical 3D single word line gain cell with shared read/write bit line | Kamal M. Karda, Haitao Liu, Karthik Sarpatwari | 2022-01-11 |