Issued Patents 2022
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11537402 | Execution elision of intermediate instruction by processor | Brian D. Barrick, Bryan Lloyd, Brian W. Thompto, Edmund J. Gieske, John B. Griswell, Jr. | 2022-12-27 |
| 11531548 | Fast perfect issue of dependent instructions in a distributed issue queue system | Brian D. Barrick, Brian W. Thompto, Tu-An T. Nguyen, Salma Ayub | 2022-12-20 |
| 11500642 | Assignment of microprocessor register tags at issue time | Steven J. Battle, Jentje Leenstra, Brian D. Barrick, Brian W. Thompto | 2022-11-15 |
| 11403109 | Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2022-08-02 |
| 11392386 | Program counter (PC)-relative load and store addressing for fused instructions | Nicholas R. Orzol, Christian Zoellin, Brian W. Thompto, Niels Fricke, Sheldon B. Levenstein +2 more | 2022-07-19 |
| 11366671 | Completion mechanism for a microprocessor instruction completion table | Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2022-06-21 |
| 11360779 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2022-06-14 |
| 11360775 | Slice-based allocation history buffer | Brian D. Barrick, Gregory W. Alexander | 2022-06-14 |
| 11327766 | Instruction dispatch routing | Eric M. Schwarz, Brian W. Thompto, Kurt A. Feiste, Michael J. Genden, Susan E. Eisen | 2022-05-10 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Kurt A. Feiste, Susan E. Eisen, Christian Zoellin, Kent Li +4 more | 2022-05-10 |
| 11301254 | Instruction streaming using state migration | Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Brian W. Thompto | 2022-04-12 |
| 11269647 | Finish status reporting for a simultaneous multithreading processor using an instruction completion table | Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Christopher M. Mueller, Tu-An T. Nguyen +2 more | 2022-03-08 |
| 11256507 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le | 2022-02-22 |
| 11249757 | Handling and fusing load instructions in a processor | Bryan Lloyd, Brian W. Thompto, Sheldon B. Levenstein, Brian D. Barrick, Christian Zoellin | 2022-02-15 |