| 11537402 |
Execution elision of intermediate instruction by processor |
Bryan Lloyd, Dung Q. Nguyen, Brian W. Thompto, Edmund J. Gieske, John B. Griswell, Jr. |
2022-12-27 |
| 11531548 |
Fast perfect issue of dependent instructions in a distributed issue queue system |
Dung Q. Nguyen, Brian W. Thompto, Tu-An T. Nguyen, Salma Ayub |
2022-12-20 |
| 11500642 |
Assignment of microprocessor register tags at issue time |
Steven J. Battle, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto |
2022-11-15 |
| 11403109 |
Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor |
Steven J. Battle, Khandker N. Adeeb, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more |
2022-08-02 |
| 11392386 |
Program counter (PC)-relative load and store addressing for fused instructions |
Nicholas R. Orzol, Christian Zoellin, Brian W. Thompto, Dung Q. Nguyen, Niels Fricke +2 more |
2022-07-19 |
| 11360779 |
Logical register recovery within a processor |
Steven J. Battle, Salma Ayub, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more |
2022-06-14 |
| 11360775 |
Slice-based allocation history buffer |
Gregory W. Alexander, Dung Q. Nguyen |
2022-06-14 |
| 11327757 |
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files |
Steven J. Battle, Kurt A. Feiste, Susan E. Eisen, Dung Q. Nguyen, Christian Zoellin +4 more |
2022-05-10 |
| 11249757 |
Handling and fusing load instructions in a processor |
Bryan Lloyd, Brian W. Thompto, Dung Q. Nguyen, Sheldon B. Levenstein, Christian Zoellin |
2022-02-15 |
