| 11403109 |
Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor |
Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more |
2022-08-02 |
| 11366671 |
Completion mechanism for a microprocessor instruction completion table |
Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh |
2022-06-21 |
| 11360779 |
Logical register recovery within a processor |
Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more |
2022-06-14 |
| 11327766 |
Instruction dispatch routing |
Eric M. Schwarz, Brian W. Thompto, Kurt A. Feiste, Michael J. Genden, Dung Q. Nguyen |
2022-05-10 |
| 11327757 |
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files |
Steven J. Battle, Kurt A. Feiste, Dung Q. Nguyen, Christian Zoellin, Kent Li +4 more |
2022-05-10 |
| 11269647 |
Finish status reporting for a simultaneous multithreading processor using an instruction completion table |
Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Christopher M. Mueller, Tu-An T. Nguyen +2 more |
2022-03-08 |
| 11256507 |
Thread transition management |
Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen |
2022-02-22 |
