| 11537519 |
Marking in-flight requests affected by translation entry invalidation in a data processing system |
Derek E. Williams, Guy L. Guthrie, Hugh Shen, David Campbell, Samuel David Kirchhoff +1 more |
2022-12-27 |
| 11537402 |
Execution elision of intermediate instruction by processor |
Brian D. Barrick, Dung Q. Nguyen, Brian W. Thompto, Edmund J. Gieske, John B. Griswell, Jr. |
2022-12-27 |
| 11520704 |
Writing store data of multiple store operations into a cache line in a single cycle |
Robert A. Cordes |
2022-12-06 |
| 11520585 |
Prefetch store preallocation in an effective address-based cache directory |
Brian W. Thompto, George W. Rohrbaugh, III, Mohit Karve, Vivek Britto |
2022-12-06 |
| 11500774 |
Virtual cache tag renaming for synonym handling |
David Campbell |
2022-11-15 |
| 11379241 |
Handling oversize store to load forwarding in a processor |
Brian Chen, Kimberly M. Fernsler, Robert A. Cordes, David A. Hrusecky |
2022-07-05 |
| 11321088 |
Tracking load and store instructions and addresses in an out-of-order processor |
Samuel David Kirchhoff, Brian Chen, Kimberly M. Fernsler, David A. Hrusecky |
2022-05-03 |
| 11314510 |
Tracking load and store instructions and addresses in an out-of-order processor |
Samuel David Kirchhoff, Brian Chen, Kimberly M. Fernsler, David A. Hrusecky |
2022-04-26 |
| 11263151 |
Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations |
David Campbell, David A. Hrusecky, Kimberly M. Fernsler, Jeffrey A. Stuecheli, Guy L. Guthrie +4 more |
2022-03-01 |
| 11249757 |
Handling and fusing load instructions in a processor |
Brian W. Thompto, Dung Q. Nguyen, Sheldon B. Levenstein, Brian D. Barrick, Christian Zoellin |
2022-02-15 |
| 11243773 |
Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges |
David Campbell, Brian Chen, Robert A. Cordes |
2022-02-08 |
