Issued Patents 2021
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11177277 | Word line architecture for three dimensional NAND flash memory | Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Toru Miwa | 2021-11-16 |
| 11081192 | Memory plane structure for ultra-low read latency applications in non-volatile memories | Hiroki Yabe, Koichiro Hayashi, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more | 2021-08-03 |
| 10991429 | Word line decoder circuitry under a three-dimensional memory array | Hiroyuki Ogawa, Fumiaki Toyama | 2021-04-27 |
| 10984874 | Differential dbus scheme for low-latency random read for NAND memories | Hiroki Yabe, Koichiro Hayashi, Naoki Ookuma, Toru Miwa | 2021-04-20 |
| 10885984 | Area effective erase voltage isolation in NAND memory | Hiroki Yabe, Koichiro Hayashi, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more | 2021-01-05 |