Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11177277 | Word line architecture for three dimensional NAND flash memory | Naoki Ookuma, Koichiro Hayashi, Takuya Ariki, Toru Miwa | 2021-11-16 |
| 11158384 | Apparatus and methods for configurable bit line isolation in non-volatile memory | — | 2021-10-26 |
| 11087800 | Sense amplifier architecture providing small swing voltage sensing | — | 2021-08-10 |
| 11081167 | Sense amplifier architecture for low supply voltage operations | Koichiro Hayashi | 2021-08-03 |
| 11081192 | Memory plane structure for ultra-low read latency applications in non-volatile memories | Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more | 2021-08-03 |
| 11004518 | Threshold voltage setting with boosting read scheme | Kiyohiko Sakakibara, Ken Oowada, Masaaki Higashitani | 2021-05-11 |
| 10984877 | Multi BLCS for multi-state verify and multi-level QPW | Jongyeon Kim, Kou Tei, Chia-Kai Chou, Ohwon Kwon | 2021-04-20 |
| 10984874 | Differential dbus scheme for low-latency random read for NAND memories | Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa | 2021-04-20 |
| 10964390 | Skip coding for fractional bit-per-cell NAND memories | — | 2021-03-30 |
| 10910044 | State coding for fractional bits-per-cell memory | Masahiro Kano | 2021-02-02 |
| 10885984 | Area effective erase voltage isolation in NAND memory | Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more | 2021-01-05 |