Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11189335 | Double write/read throughput by CMOS adjacent array (CaA) NAND memory | Masatoshi Nishikawa, Hardwell Chibvongodze | 2021-11-30 |
| 11094715 | Three-dimensional memory device including different height memory stack structures and methods of making the same | Zhixin Cui, Masatoshi Nishikawa | 2021-08-17 |
| 11049580 | Modulation of programming voltage during cycling | Rajdeep Gautam | 2021-06-29 |
| 11024393 | Read operation for non-volatile memory with compensation for adjacent wordline | Zhiping Zhang, Huai-Yuan Tseng, Deepanshu Dutta | 2021-06-01 |
| 11004518 | Threshold voltage setting with boosting read scheme | Kiyohiko Sakakibara, Hiroki Yabe, Masaaki Higashitani | 2021-05-11 |
| 11004525 | Modulation of programming voltage during cycling | Rajdeep Gautam | 2021-05-11 |
| 10978156 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Toru Miwa | 2021-04-13 |
| 10978152 | Adaptive VPASS for 3D flash memory with pair string structure | Rajdeep Gautam, Hardwell Chibvongodze | 2021-04-13 |
| 10971231 | Adaptive VPASS for 3D flash memory with pair string structure | Rajdeep Gautam, Hardwell Chibvongodze | 2021-04-06 |
| 10957401 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Masaaki Higashitani | 2021-03-23 |
| 10950311 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Masaaki Higashitani | 2021-03-16 |