Issued Patents 2021
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11201111 | Three-dimensional memory device containing structures for enhancing gate-induced drain leakage current and methods of forming the same | Dengtao Zhao, Zhiping Zhang, Peng Zhang | 2021-12-14 |
| 11189337 | Multi-stage voltage control for peak and average current reduction of open blocks | Yu-Chung Lien, Huai-Yuan Tseng | 2021-11-30 |
| 11177002 | Programming memory cells using encoded TLC-fine | Xue Bai Pitner, Ravi Kumar | 2021-11-16 |
| 11139038 | Neighboring or logical minus word line dependent verify with sense time in programming of non-volatile memory | Muhammad Masuduzzaman, Huai-Yuan Tseng | 2021-10-05 |
| 11107901 | Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same | Yu-Chung Lien, Jiahui Yuan | 2021-08-31 |
| 11081180 | Memory device with bit lines disconnected from NAND strings for fast programming | Xiang Yang, Huai-Yuan Tseng | 2021-08-03 |
| 11081184 | Method of concurrent multi-state programming of non-volatile memory with bit line voltage step up | Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao | 2021-08-03 |
| 11062780 | System and method of reading two pages in a nonvolatile memory | Zhiping Zhang, Huai-Yuan Tseng, Jiahui Yuan, Dengtao Zhao | 2021-07-13 |
| 11024393 | Read operation for non-volatile memory with compensation for adjacent wordline | Zhiping Zhang, Huai-Yuan Tseng, Ken Oowada | 2021-06-01 |
| 11017869 | Programming process combining adaptive verify with normal and slow programming speeds in a memory device | Xiang Yang, Huai-Yuan Tseng | 2021-05-25 |
| 11011242 | Bit line voltage control for damping memory programming | Xiang Yang, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li | 2021-05-18 |
| 10984867 | Direct look ahead mode for memory apparatus programmed with reverse order programming | Zhiping Zhang, Sarath Chandran Puthen Thermadam, Huai-Yuan Tseng | 2021-04-20 |
| 10930355 | Row dependent sensing in nonvolatile memory | Xiang Yang, Huai-Yuan Tseng | 2021-02-23 |
| 10910069 | Manage source line bias to account for non-uniform resistance of memory cell source lines | Murong Lang, Zhenming Zhou | 2021-02-02 |
| 10910075 | Programming process combining adaptive verify with normal and slow programming speeds in a memory device | Xiang Yang, Huai-Yuan Tseng | 2021-02-02 |
| 10902925 | Peak and average current reduction for open block condition | Yu-Chung Lien, Michael Tseng | 2021-01-26 |
| 10885994 | Interleaved program and verify in non-volatile memory | Xiang Yang, Huai-Yuan Tseng | 2021-01-05 |