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Christopher John Kawamura — 19 Patents in 2021

Micron: 18 patents #30 of 1,454Top 3%

Boise, ID: #9 of 667 inventorsTop 2%

Idaho: #11 of 1,226 inventorsTop 1%

Overall (2021): #2,214 of 548,734Top 1%

19 Patents 2021

Issued Patents 2021

Showing 1–19 of 19 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11211113	Integrated assemblies comprising wordlines having ends selectively shunted to low voltage for speed transitioning	Scott J. Derner	2021-12-28	$20,140,000
11205468	Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory	Scott J. Derner	2021-12-21	$35,688,000
11200937	Reprogrammable non-volatile ferroelectric latch for use with a memory controller	Scott J. Derner, Charles L. Ingalls	2021-12-14	$22,879,000
11176987	Dram array architecture with row hammer stress mitigation	Charles L. Ingalls, Tae H. Kim	2021-11-16	$19,987,000
11176978	Apparatuses and method for reducing row address to column address delay	—	2021-11-16	$19,987,000
11127450	Pre-writing memory cells of an array	Scott J. Derner	2021-09-21	$21,559,000
11120847	Apparatuses and method for reducing row address to column address delay for a voltage threshold compensation sense amplifier	Tae H. Kim	2021-09-14
11107515	Ferroelectric memory cells	Scott J. Derner	2021-08-31	$19,408,000
11074964	Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation	Jiyun Li	2021-07-27	$20,745,000
11056165	Cell-specific reference generation and sensing	Scott J. Derner	2021-07-06	$20,168,000
11017832	Multi-level storage in ferroelectric memory	—	2021-05-25	$23,972,000
10998031	Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory	Scott J. Derner	2021-05-04	$18,454,000
10978138	Main word line driver circuit	Tae H. Kim	2021-04-13	$23,307,000
10950286	Periphery fill and localized capacitance	Scott J. Derner	2021-03-16	$22,312,000
10910379	Integrated assemblies comprising memory cells and shielding material between the memory cells, and methods of forming integrated assemblies	Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Hiroaki Taketani	2021-02-02	$21,204,000
10910038	DRAM array architecture with row hammer stress mitigation	Charles L. Ingalls, Tae H. Kim	2021-02-02	$21,204,000
10902899	Apparatuses and method for reducing row address to column address delay	—	2021-01-26	$25,472,000
10896717	Pseudo-non-volatile memory cells	Scott J. Derner	2021-01-19	$23,715,000
10885964	Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory	Scott J. Derner	2021-01-05	$21,674,000