| 11200937 |
Reprogrammable non-volatile ferroelectric latch for use with a memory controller |
Scott J. Derner, Christopher John Kawamura |
2021-12-14 |
| 11176987 |
Dram array architecture with row hammer stress mitigation |
Christopher John Kawamura, Tae H. Kim |
2021-11-16 |
| 11062753 |
Array data bit inversion |
Scott J. Derner |
2021-07-13 |
| 11031400 |
Integrated memory comprising secondary access devices between digit lines and primary access devices |
Scott J. Derner |
2021-06-08 |
| 10998027 |
Memory circuitry |
Scott J. Derner, Tae H. Kim |
2021-05-04 |
| 10957382 |
Integrated assemblies comprising vertically-stacked memory array decks and folded digit line connections |
Scott J. Derner |
2021-03-23 |
| 10957681 |
Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array |
Hiroki Fujisawa, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner |
2021-03-23 |
| 10943642 |
Integrated memory assemblies comprising multiple memory array decks |
Scott J. Derner |
2021-03-09 |
| 10930653 |
Apparatuses comprising memory cells, and apparatuses comprising memory arrays |
Scott J. Derner, Michael A. Shore, Steve V. Cole |
2021-02-23 |
| 10916548 |
Memory arrays with vertical access transistors |
Scott J. Derner |
2021-02-09 |
| 10916295 |
Memory arrays with vertical thin film transistors coupled between digit lines |
Scott J. Derner |
2021-02-09 |
| 10910049 |
Sub-word line driver circuit |
Tae H. Kim |
2021-02-02 |
| 10910038 |
DRAM array architecture with row hammer stress mitigation |
Christopher John Kawamura, Tae H. Kim |
2021-02-02 |
| 10896706 |
FX driver circuit |
Tae H. Kim |
2021-01-19 |
| 10896722 |
Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure |
Jiyun Li |
2021-01-19 |
