Issued Patents 2021
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11200119 | Low latency availability in degraded redundant array of independent memory | Glenn D. Gilda, David D. Cadigan, Lawrence W. Jones | 2021-12-14 |
| 11088782 | Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection | Steven R. Carlough, Gary A. Van Huben | 2021-08-10 |
| 10976939 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2021-04-13 |
| 10901839 | Common high and low random bit error correction logic | James A. O'Connor, Barry M. Trager, Warren E. Maule, Brad W. Michael, Marc A. Gollub | 2021-01-26 |