Issued Patents 2021
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11010192 | Register restoration using recovery buffers | Chung-Lung K. Shum, Timothy J. Slegel | 2021-05-18 |
| 11010276 | Configurable code fingerprint | Giles R. Frazier, Christian Jacobi, Chung-Lung K. Shum | 2021-05-18 |
| 11003452 | Effectiveness and prioritization of prefetches | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2021-05-11 |
| 10996982 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2021-05-04 |
| 10977185 | Initializing a data structure for use in predicting table of contents pointer values | Valentina Salapura | 2021-04-13 |
| 10976931 | Automatic pinning of units of memory | Valentina Salapura | 2021-04-13 |
| 10963261 | Sharing snapshots across save requests | Valentina Salapura | 2021-03-30 |
| 10963382 | Table of contents cache entry having a pointer for a range of addresses | Valentina Salapura | 2021-03-30 |
| 10956340 | Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size | Anthony J. Bybell, Bradly G. Frey | 2021-03-23 |
| 10949221 | Executing instructions to store context information based on routine to be executed | — | 2021-03-16 |
| 10949350 | Table of contents cache entry having a pointer for a range of addresses | Valentina Salapura | 2021-03-16 |
| 10936314 | Suppressing branch prediction on a repeated execution of an aborted transaction | Valentina Salapura, Chung-Lung K. Shum | 2021-03-02 |
| 10929297 | Prefetch protocol for transactional memory | Valentina Salapura, Chung-Lung K. Shum | 2021-02-23 |
| 10929135 | Predicting and storing a predicted target address in a plurality of selected locations | Valentina Salapura | 2021-02-23 |
| 10915439 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2021-02-09 |
| 10908911 | Predicting and storing a predicted target address in a plurality of selected locations | Valentina Salapura | 2021-02-02 |
| 10901741 | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence | Valentina Salapura | 2021-01-26 |
| 10901738 | Bulk store and load operations of configuration state registers | Valentina Salapura | 2021-01-26 |
| 10896040 | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence | — | 2021-01-19 |
| 10896030 | Code generation relating to providing table of contents pointer values | Valentina Salapura | 2021-01-19 |
| 10891130 | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence | — | 2021-01-12 |
| 10891133 | Code-specific affiliated register prediction | Valentina Salapura | 2021-01-12 |
| 10884748 | Providing a predicted target address to multiple locations based on detecting an affiliated relationship | Valentina Salapura | 2021-01-05 |
| 10884931 | Interprocessor memory status communication | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2021-01-05 |
| 10884930 | Set table of contents (TOC) register instruction | Valentina Salapura | 2021-01-05 |