Issued Patents 2021
Showing 1–25 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11194580 | Selective suppression of instruction translation lookaside buffer (ITLB) access | Valentina Salapura | 2021-12-07 |
| 11182198 | Indicator-based prioritization of transactions | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Eric M. Schwarz, Timothy Siegel | 2021-11-23 |
| 11150908 | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence | Valentina Salapura | 2021-10-19 |
| 11150904 | Concurrent prediction of branch addresses and update of register contents | Valentina Salapura | 2021-10-19 |
| 11144320 | Selective suppression of instruction cache-related directory access | Valentina Salapura | 2021-10-12 |
| 11138113 | Set table of contents (TOC) register instruction | Valentina Salapura | 2021-10-05 |
| 11138127 | Initializing a data structure for use in predicting table of contents pointer values | Valentina Salapura | 2021-10-05 |
| 11132290 | Locality domain-based memory pools for virtualized computing environment | — | 2021-09-28 |
| 11119942 | Facilitating access to memory locality domain information | Jonathan D. Bradbury | 2021-09-14 |
| 11119785 | Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed | Valentina Salapura | 2021-09-14 |
| 11106490 | Context switch by changing memory pointers | Valentina Salapura | 2021-08-31 |
| 11099782 | Portions of configuration state registers in-memory | Valentina Salapura | 2021-08-24 |
| 11093145 | Protecting in-memory configuration state registers | Valentina Salapura | 2021-08-17 |
| 11080052 | Determining the effectiveness of prefetch instructions | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2021-08-03 |
| 11061575 | Read-only table of contents register | Valentina Salapura | 2021-07-13 |
| 11061576 | Read-only table of contents register | Valentina Salapura | 2021-07-13 |
| 11061684 | Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination | Chung-Lung K. Shum, Timothy J. Slegel | 2021-07-13 |
| 11048635 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Christian Jacobi, Chung-Lung K. Shum | 2021-06-29 |
| 11036519 | Simultaneously capturing status information for multiple operating modes | Brett Olsson | 2021-06-15 |
| 11036513 | Executing short pointer mode applications loaded in a memory address space having one portion addressable by short pointers and a shadow copy of the one portion | — | 2021-06-15 |
| 11029974 | Architectural mode configuration | Charles W. Gainey, Jr. | 2021-06-08 |
| 11023256 | Architectural mode configuration | Charles W. Gainey, Jr. | 2021-06-01 |
| 11016744 | Context information based on type of routine being called | — | 2021-05-25 |
| 11010192 | Register restoration using recovery buffers | Chung-Lung K. Shum, Timothy J. Slegel | 2021-05-18 |
| 11010276 | Configurable code fingerprint | Giles R. Frazier, Christian Jacobi, Chung-Lung K. Shum | 2021-05-18 |