Issued Patents 2020
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878918 | Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit | Pascal Fornara | 2020-12-29 |
| 10861802 | Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit | Pascal Fornara, Guilhem Bouton, Mathieu Lisart | 2020-12-08 |
| 10804222 | Integrated circuit containing a decoy structure formed by an electrically insulated silicide sector | Julien Delalleau | 2020-10-13 |
| 10796992 | Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit | Jean-Philippe Escales | 2020-10-06 |
| 10797158 | Transistor comprising a lengthened gate | Julien Delalleau | 2020-10-06 |
| 10770409 | Method for detecting thinning of the substrate of an integrated circuit from its back side, and associated integrated circuit | Abderrezak Marzaki, Quentin Hubert | 2020-09-08 |
| 10770547 | Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses | Guilhem Bouton, Pascal Fornara | 2020-09-08 |
| 10763213 | Integrated circuit having a hidden shared contact | Julien Delalleau | 2020-09-01 |
| 10748726 | Integrated mechanical device with vertical movement | Pascal Fornara, Antonio Di-Giacomo, Brice Arrazat | 2020-08-18 |
| 10714583 | MOS transistor with reduced hump effect | Guilhem Bouton, Pascal Fornara, Julien Delalleau | 2020-07-14 |
| 10685912 | Integrated circuit comprising an antifuse structure and method of realizing | Pascal Fornara | 2020-06-16 |
| 10600737 | Prevention of premature breakdown of interline porous dielectrics in an integrated circuit | Pascal Fornara, Jean-Philippe Escales | 2020-03-24 |
| 10593772 | Double-gate MOS transistor with increased breakdown voltage | Julien Delalleau | 2020-03-17 |
| 10580498 | Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit | Pascal Fornara | 2020-03-03 |