Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10833100 | Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same | Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano | 2020-11-10 |
| 10811058 | Bonded assembly containing memory die bonded to integrated peripheral and system die and methods for making the same | Yanli Zhang, Zhixin Cui, Johann Alsmeier, Yan Li, Steven T. Sprouse | 2020-10-20 |
| 10804202 | Bonded assembly including a semiconductor-on-insulator die and methods for making the same | — | 2020-10-13 |
| 10797061 | Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same | Toshihiro Iizuka, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou +1 more | 2020-10-06 |
| 10797060 | Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same | Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan +1 more | 2020-10-06 |
| 10797062 | Bonded die assembly using a face-to-back oxide bonding and methods for making the same | Masatoshi Nishikawa | 2020-10-06 |
| 10797070 | Three-dimensional memory device containing a replacement buried source line and methods of making the same | Mitsuteru Mushiga, Kenji Sugiura | 2020-10-06 |
| 10741576 | Three-dimensional memory device containing drain-select-level air gap and methods of making the same | Masatoshi Nishikawa | 2020-08-11 |
| 10714497 | Three-dimensional device with bonded structures including a support die and methods of making the same | Mitsuteru Mushiga | 2020-07-14 |
| 10700028 | Vertical chip interposer and method of making a chip assembly containing the vertical chip interposer | — | 2020-06-30 |
| 10665607 | Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same | Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano | 2020-05-26 |
| 10665580 | Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same | Naohiro Hosoda, Kazuma Shimamoto, Tetsuya Shirasu, Yuji Fukano | 2020-05-26 |