Issued Patents 2020
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10804166 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-10-13 |
| 10741554 | Third type of metal gate stack for CMOS devices | Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman | 2020-08-11 |
| 10707224 | FinFET vertical flash memory | Arvind Kumar, Carl Radens | 2020-07-07 |
| 10707332 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2020-07-07 |
| 10600877 | Fully depleted SOI device for reducing parasitic back gate capacitance | Kangguo Cheng | 2020-03-24 |
| 10586799 | Multiple-bit electrical fuses | Kangguo Cheng | 2020-03-10 |
| 10559662 | Hybrid aspect ratio trapping | Kangguo Cheng, Hong He, Juntao Li | 2020-02-11 |
| 10541177 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-01-21 |