Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10852806 | Dual path sequential element to reduce toggles in data path | Subramaniam Maiyuran, Sanjeev Jahagirdar, Eric J. Asperheim, Altug Koker, Balaji Vembu +2 more | 2020-12-01 |
| 10831598 | Bypassing error correction code (ECC) processing based on software hint | Altug Koker, Abhishek R. Appu, Joydeep Ray | 2020-11-10 |
| 10817296 | Message based general register file assembly | Abhishek R. Appu, Altug Koker, Joydeep Ray, Ramkumar Ravikumar, Prasoonkumar Surti +1 more | 2020-10-27 |
| 10783084 | Sector cache for compression | Abhishek R. Appu, Atlug Koker, Joydeep Ray, David Puffer, Prasoonkumar Surti +4 more | 2020-09-22 |
| 10769072 | Avoid cache lookup for cold cache | Abhishek R. Appu, Altug Koker, Joydeep Ray, Prasoonkumar Surti, Kamal Sinha +1 more | 2020-09-08 |
| 10769818 | Smart compression/decompression schemes for efficiency and superior results | Abhishek R. Appu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay | 2020-09-08 |
| 10761589 | Interconnect fabric link width reduction to reduce instantaneous power consumption | Mohammed Tameem, Altug Koker, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray +2 more | 2020-09-01 |
| 10691497 | High bandwidth connection between processor dies | Altug Koker, Abhishek R. Appu, Joydeep Ray, Balaji Vembu | 2020-06-23 |
| 10691392 | Regional adjustment of render rate | Eric J. Asperheim, Subramaniam Maiyuran, Sanjeev Jahagirdar, Balaji Vembu, Devan Burke +11 more | 2020-06-23 |
| 10621109 | Memory access compression using clear code for tile pixels | Prasoonkumar Surti, Abhishek R. Appu | 2020-04-14 |
| 10579121 | Processor power management | Altug Koker, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti +8 more | 2020-03-03 |
| 10558254 | Power consumption management for communication bus | Abhishek R. Appu, Altug Koker, Eric J. Hoekstra, Prasoonkumar Surti, Vasanth Ranganathan +5 more | 2020-02-11 |