| 10871966 |
Intelligent thread dispatch and vectorization of atomic operations |
Feng Chen, Narayan Srinivasa, Abhishek R. Appu, Altug Koker, Kamal Sinha +6 more |
2020-12-22 |
| 10852806 |
Dual path sequential element to reduce toggles in data path |
Subramaniam Maiyuran, Kiran C. Veernapu, Eric J. Asperheim, Altug Koker, Balaji Vembu +2 more |
2020-12-01 |
| 10817042 |
Power savings for neural network architecture with zero activations during inference |
Kinchit Desai, Prasoonkumar Surti, Joydeep Ray |
2020-10-27 |
| 10803548 |
Disaggregation of SOC architecture |
Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Altug Koker +6 more |
2020-10-13 |
| 10761898 |
Migrating threads between asymmetric cores in a multiple core processor |
Varghese George, Inder M. Sodhi |
2020-09-01 |
| 10747286 |
Dynamic power budget allocation in multi-processor system |
Nikos Kaburlasos, Iqbal Rajwani, Bhushan M. Borole, Kamal Sinha |
2020-08-18 |
| 10740281 |
Asymmetric performance multicore architecture with same instruction set architecture |
Varghese George, Deborah T. Marr |
2020-08-11 |
| 10691392 |
Regional adjustment of render rate |
Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Balaji Vembu, Devan Burke +11 more |
2020-06-23 |
| 10671133 |
Configurable power supplies for dynamic current sharing |
Sandeep K. Venishetti, Srinivas Thota |
2020-06-02 |
| 10558254 |
Power consumption management for communication bus |
Abhishek R. Appu, Altug Koker, Eric J. Hoekstra, Kiran C. Veernapu, Prasoonkumar Surti +5 more |
2020-02-11 |