Issued Patents 2020
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831954 | Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs | Ravi Chander LEDALLA, Chaobo Li, Adil Bhanji, Gregory M. Schaeffer, Michael H. Wood | 2020-11-10 |
| 10747925 | Variable accuracy incremental timing analysis | Jeffrey G. Hemmett, Kerim Kalafala, Natesan Venkateswaran, Eric A. Foreman, Chaitanya Ravindra Peddawad | 2020-08-18 |