Issued Patents 2020
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831954 | Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs | Debjit Sinha, Ravi Chander LEDALLA, Chaobo Li, Gregory M. Schaeffer, Michael H. Wood | 2020-11-10 |