Issued Patents 2020
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831954 | Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs | Debjit Sinha, Ravi Chander LEDALLA, Chaobo Li, Adil Bhanji, Gregory M. Schaeffer | 2020-11-10 |
| 10691853 | Superposition of canonical timing value representations in statistical static timing analysis | Eric A. Foreman, James C. Gregerson, Gregory M. Schaeffer | 2020-06-23 |