Issued Patents 2020
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831954 | Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs | Debjit Sinha, Ravi Chander LEDALLA, Chaobo Li, Adil Bhanji, Michael H. Wood | 2020-11-10 |
| 10691853 | Superposition of canonical timing value representations in statistical static timing analysis | Eric A. Foreman, James C. Gregerson, Michael H. Wood | 2020-06-23 |
| 10606970 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Stephen G. Shuma, Alexander J. Suess +3 more | 2020-03-31 |