Issued Patents 2020
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10705588 | Enabling a non-core domain to control memory bandwidth in a processor | Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Ryan D. Wells | 2020-07-07 |
| 10678319 | Multi-level loops for computer processor control | Doron Rajwan, Efraim Rotem, Avinash N. Ananthakrishnan, Dorit Shapira | 2020-06-09 |
| 10620682 | System, apparatus and method for processor-external override of hardware performance state control of a processor | Nikhil Gupta, Israel Hirsh, Esfir Natanzon, Nir Rosenzweig, Efraim Rotem +2 more | 2020-04-14 |
| 10613614 | Dynamically controlling cache size to maximize energy efficiency | Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more | 2020-04-07 |
| 10564699 | Dynamically controlling cache size to maximize energy efficiency | Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more | 2020-02-18 |
| 10558490 | Mechanism for issuing requests to an accelerator from multiple threads | Ronny Ronen, Boris Ginzburg | 2020-02-11 |
| 10545793 | Thread scheduling using processing engine information | Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov +6 more | 2020-01-28 |