AV

Abhishek Venkatesh

IN Intel: 13 patents #115 of 5,492Top 3%
Overall (2020): #5,610 of 565,922Top 1%
13
Patents 2020

Issued Patents 2020

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
10867427 Multi-resolution image plane rendering within an improved graphics processor microarchitecture Michael Apodaca, Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Jonathan Kennedy +1 more 2020-12-15
10861126 Asynchronous execution mechanism Saurabh Sharma, Michael Apodaca, Aditya Navale, Travis T. Schluessler, Vamsee Vardhan Chivukula +1 more 2020-12-08
10803656 Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Joydeep Ray +1 more 2020-10-13
10796397 Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices James Valerio, Satyajit Sarangi, Michael Apodaca, Thomas Raoux, Hashem Hashemi +1 more 2020-10-06
10783603 Graphics processor with tiled compute kernels Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak +2 more 2020-09-22
10748238 Frequent data value compression for graphics processing units Saurabh Sharma, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh Anantaraman +9 more 2020-08-18
10733690 GPU mixed primitive topology type processing John G. Gierach, Travis T. Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca 2020-08-04
10728492 Synergistic temporal anti-aliasing and coarse pixel shading technology Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski +4 more 2020-07-28
10706612 Tile-based immediate mode rendering with early hierarchical-z Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini +4 more 2020-07-07
10706591 Controlling coarse pixel size from a stencil buffer Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp +3 more 2020-07-07
10643374 Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp +15 more 2020-05-05
10573066 Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Joydeep Ray +1 more 2020-02-25
10540260 Dynamic instruction latency management in SIMD machines Travis T. Schluessler, Elmoustapha Ould-Ahmed-Vall, John G. Gierach, Tomer Bar On, Devan Burke 2020-01-21