Issued Patents 2020
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10816599 | Dynamically power noise adaptive automatic test pattern generation | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Sumit Panigrahi | 2020-10-27 |
| 10768230 | Built-in device testing of integrated circuits | Robert M. Casatuta, Gary W. Maier, Franco Motika, Phong T. Tran | 2020-09-08 |
| 10746794 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2020-08-18 |
| 10739401 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2020-08-11 |
| 10649028 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2020-05-12 |
| 10613142 | Non-destructive recirculation test support for integrated circuits | Franco Motika, Gerard M. Salem | 2020-04-07 |
| 10598727 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Cedric Lichtenau, Srinivas V. N. Polisetty | 2020-03-24 |
| 10585142 | Functional diagnostics based on dynamic selection of alternate clocking | Franco Motika, Gerard M. Salem | 2020-03-10 |
| 10545190 | Circuit structures to resolve random testability | Raghu G. GopalaKrishnaSetty, Spencer K. Millican | 2020-01-28 |
| 10545188 | Functional diagnostics based on dynamic selection of alternate clocking | Franco Motika, Gerard M. Salem | 2020-01-28 |
| 10527674 | Circuit structures to resolve random testability | Raghu G. GopalaKrishnaSetty, Spencer K. Millican | 2020-01-07 |