Issued Patents 2020
Showing 51–57 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10572384 | Operating different processor cache levels | Simon H. Friedmann, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito | 2020-02-25 |
| 10572254 | Instruction to query cache residency | Dan F. Greiner, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2020-02-25 |
| 10558465 | Restricted instructions in transactional execution | Dan F. Greiner, Timothy J. Slegel | 2020-02-11 |
| 10558552 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Chung-Lung K. Shum | 2020-02-11 |
| 10558464 | Infinite processor thread balancing | Gregory W. Alexander, Stephen Duffy, David S. Hutton, Anthony Saporito, Somin Song | 2020-02-11 |
| 10528482 | Cache management | Deanna Postles Dunn Berger, Martin Recktenwald, Yossi Shapira, Aaron Tsai | 2020-01-07 |
| 10528472 | Method and arrangement for saving cache power | Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2020-01-07 |