Issued Patents 2020
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10684863 | Restricted instructions in transactional execution | Dan F. Greiner, Timothy J. Slegel | 2020-06-16 |
| 10684951 | Minimizing cache latencies using set predictors | Dwifuzi Coe, Markus Kaltenbach, Eyal Naor, Martin Recktenwald | 2020-06-16 |
| 10671532 | Reducing cache transfer overhead in a system | Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2020-06-02 |
| 10671390 | Conditional instruction end operation | Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2020-06-02 |
| 10673460 | Spilling temporary results for accommodation of memory boundaries | Girish G. Kurup, Matthias Klein, Anthony T. Sofia, Jonathan D. Bradbury, Ashutosh Misra +1 more | 2020-06-02 |
| 10657059 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum | 2020-05-19 |
| 10656950 | Spin loop delay instruction | Fadi Y. Busaba, Anthony Saporito, Eric M. Schwarz, Timothy J. Slegel | 2020-05-19 |
| 10656945 | Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction | Chung-Lung Kevin Chum, Timothy J. Slegel, Gustav E. Sittmann, III | 2020-05-19 |
| 10649778 | Performance optimized congruence class matching for multiple concurrent radix translations | David Campbell, Dwain A. Hicks, Kerey Michelle Tassin | 2020-05-12 |
| 10635592 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum | 2020-04-28 |
| 10635603 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Markus Kaltenbach, Thomas Koehler, Frank Lehnert | 2020-04-28 |
| 10621105 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Markus Kaltenbach, Thomas Koehler, Frank Lehnert | 2020-04-14 |
| 10621090 | Facility for extending exclusive hold of a cache line in private cache | Bruce C. Giamei, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum | 2020-04-14 |
| 10606762 | Sharing virtual and real translations in a virtual cache | Markus Helms, Martin Recktenwald, Johannes C. Reichart | 2020-03-31 |
| 10606597 | Nontransactional store instruction | Dan F. Greiner, Timothy J. Slegel | 2020-03-31 |
| 10599431 | Managing backend resources via frontend steering or stalls | Gregory W. Alexander, David S. Hutton, Edward T. Malley, Anthony Saporito | 2020-03-24 |
| 10599435 | Nontransactional store instruction | Dan F. Greiner, Timothy J. Slegel | 2020-03-24 |
| 10592142 | Toggling modal transient memory access state | Michael K. Gschwind, Younes Manton, Anthony Saporito, Timothy J. Slegel | 2020-03-17 |
| 10585800 | Reducing cache transfer overhead in a system | Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2020-03-10 |
| 10585797 | Operating different processor cache levels | Simon H. Friedmann, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito | 2020-03-10 |
| 10579377 | Guarded storage event handling during transactional execution | Dan F. Greiner, Volodymyr Paprotski, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2020-03-03 |
| 10579525 | Reducing cache transfer overhead in a system | Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2020-03-03 |
| 10579514 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2020-03-03 |
| 10579499 | Task latency debugging in symmetric multiprocessing computer systems | Eberhard Engler, Timothy J. Slegel, Scott Barnett Swaney | 2020-03-03 |
| 10579332 | Hardware sort accelerator sharing first level processor cache | Aditya N. Puranik, Martin Recktenwald, Christian Zoellin | 2020-03-03 |