SG

Steven Lee Gregor

CS Cadence Design Systems: 6 patents #4 of 328Top 2%
📍 Owego, NY: #1 of 9 inventorsTop 15%
🗺 New York: #690 of 13,306 inventorsTop 6%
Overall (2020): #22,245 of 565,922Top 4%
6
Patents 2020

Issued Patents 2020

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
10783299 Simulation event reduction and power control during MBIST through clock tree management Puneet Arora, Norman Robert Card 2020-09-22
10706950 Testing for memory error correction code logic Patrick Gallagher 2020-07-07
10706952 Testing for memories during mission mode self-test Patrick Gallagher 2020-07-07
10699795 System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property cores Norman Robert Card 2020-06-30
10593419 Failing read count diagnostics for memory built-in self-test Puneet Arora, Norman Robert Card 2020-03-17
10541043 On demand data stream controller for programming and executing operations in an integrated circuit Carl Wisnesky, II, Patrick Gallagher, Norman Robert Card 2020-01-21