PA

Puneet Arora

CS Cadence Design Systems: 2 patents #41 of 328Top 15%
📍 Atrauli, TX: #2 of 2 inventorsTop 100%
Overall (2020): #131,360 of 565,922Top 25%
2
Patents 2020

Issued Patents 2020

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10783299 Simulation event reduction and power control during MBIST through clock tree management Steven Lee Gregor, Norman Robert Card 2020-09-22
10593419 Failing read count diagnostics for memory built-in self-test Steven Lee Gregor, Norman Robert Card 2020-03-17