| 10523599 |
Buffer sizing of a NoC through machine learning |
Eric Norige, Nishant Rao |
2019-12-31 |
| 10496770 |
System level simulation in Network on Chip architecture |
Amit Patankar, Eric Norige |
2019-12-03 |
| 10472581 |
Process and apparatus for hydrocracking and hydroisomerizing a hydrocarbon stream |
Andrew J. Towarnicky, Vasant P. Thakkar, Massimo Sangalli, John A. Petri |
2019-11-12 |
| 10469338 |
Cost management against requirements for the generation of a NoC |
William John Bainbridge, Eric Norige, Nishant Rao |
2019-11-05 |
| 10469337 |
Cost management against requirements for the generation of a NoC |
William John Bainbridge, Eric Norige, Nishant Rao |
2019-11-05 |
| 10452124 |
Systems and methods for facilitating low power on a network-on-chip |
James Bauman, Joe Rowlands |
2019-10-22 |
| 10419300 |
Cost management against requirements for the generation of a NoC |
William John Bainbridge, Eric Norige, Nishant Rao |
2019-09-17 |
| 10355996 |
Heterogeneous channel capacities in an interconnect |
Joji Philip, Eric Norige, Sundari Mitra |
2019-07-16 |
| 10348563 |
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology |
Nishant Rao, Pier Giorgio Raponi |
2019-07-09 |
| 10324509 |
Automatic generation of power management sequence in a SoC or NoC |
Anup Gangwar, Vishnu Mohan Pusuluri, Poonacha Kongetira |
2019-06-18 |
| 10298485 |
Systems and methods for NoC construction |
Pier Giorgio Raponi, Nishant Rao |
2019-05-21 |
| 10218580 |
Generating physically aware network-on-chip design from a physical system-on-chip specification |
Rajesh Chopra, Yang Lin |
2019-02-26 |
| 10218581 |
Generation of network-on-chip layout based on user specified topological constraints |
Pier Giorgio Raponi, Eric Norige |
2019-02-26 |