| 10523599 |
Buffer sizing of a NoC through machine learning |
Nishant Rao, Sailesh Kumar |
2019-12-31 |
| 10496770 |
System level simulation in Network on Chip architecture |
Sailesh Kumar, Amit Patankar |
2019-12-03 |
| 10469337 |
Cost management against requirements for the generation of a NoC |
William John Bainbridge, Sailesh Kumar, Nishant Rao |
2019-11-05 |
| 10469338 |
Cost management against requirements for the generation of a NoC |
William John Bainbridge, Sailesh Kumar, Nishant Rao |
2019-11-05 |
| 10419300 |
Cost management against requirements for the generation of a NoC |
William John Bainbridge, Sailesh Kumar, Nishant Rao |
2019-09-17 |
| 10355996 |
Heterogeneous channel capacities in an interconnect |
Sailesh Kumar, Joji Philip, Sundari Mitra |
2019-07-16 |
| 10218581 |
Generation of network-on-chip layout based on user specified topological constraints |
Pier Giorgio Raponi, Sailesh Kumar |
2019-02-26 |