Issued Patents 2019
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-12-03 |
| 10489253 | On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor | Steven J. Battle, Joshua W. Bowman, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-11-26 |
| 10445100 | Broadcasting messages between execution slices for issued instructions indicating when execution results are ready | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Dhivya Jeganathan, Dung Q. Nguyen +2 more | 2019-10-15 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-09-10 |
| 10379867 | Asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle +2 more | 2019-08-13 |
| 10318356 | Operation of a multi-slice processor implementing a hardware level transfer of an execution thread | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-06-11 |
| 10318419 | Flush avoidance in a load store unit | David A. Hrusecky, Elizabeth A. McGlone, George W. Rohrbaugh, III, Shih-Hsiung S. Tung | 2019-06-11 |
| 10282207 | Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction | Brian D. Barrick, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana +2 more | 2019-05-07 |
| 10268518 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone | 2019-04-23 |
| 10268482 | Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction | Brian D. Barrick, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana +2 more | 2019-04-23 |
| 10255107 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone | 2019-04-09 |
| 10248421 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-04-02 |
| 10241790 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-03-26 |
| 10223196 | ECC scrubbing method in a multi-slice microprocessor | Brian D. Barrick, James Wilson Bishop, Maarten J. Boersma, Marcy E. Byers, Jentje Leenstra +2 more | 2019-03-05 |
| 10223125 | Linkable issue queue parallel execution slice processing method | Jeffrey C. Brownscheidle, Maureen A. Delaney, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2019-03-05 |
| 10209995 | Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions | Richard J. Eickemeyer, John B. Griswell, Jr., Dung Q. Nguyen | 2019-02-19 |
| 10175985 | Mechanism for using a reservation station as a scratch register | Michael J. Genden, Dung Q. Nguyen | 2019-01-08 |