Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10417002 | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses | Bryan Lloyd, Balaram Sinharoy | 2019-09-17 |
| 10324856 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Bryan Lloyd, Balaram Sinharoy | 2019-06-18 |
| 10318419 | Flush avoidance in a load store unit | Sundeep Chadha, David A. Hrusecky, Elizabeth A. McGlone, George W. Rohrbaugh, III | 2019-06-11 |
| 10310988 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Bryan Lloyd, Balaram Sinharoy | 2019-06-04 |