Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10387162 | Effective address table with multiple taken branch handling for out-of-order processors | Balaram Sinharoy | 2019-08-20 |
| 10379857 | Dynamic sequential instruction prefetching | Sheldon B. Levenstein, David S. Levitan, Mauricio J. Serrano, Brian W. Thompto | 2019-08-13 |
| 10353710 | Techniques for predicting a target address of an indirect branch instruction | Naga P. Gorti, David S. Levitan, Albert J. Van Norstrand, Jr. | 2019-07-16 |
| 10209995 | Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions | Sundeep Chadha, John B. Griswell, Jr., Dung Q. Nguyen | 2019-02-19 |
| 10191847 | Prefetch performance | Bernard C. Drerup, Guy L. Guthrie, Mohit Karve, George W. Rohrbaugh, III, Brian W. Thompto | 2019-01-29 |
| 10191845 | Prefetch performance | Bernard C. Drerup, Guy L. Guthrie, Mohit Karve, George W. Rohrbaugh, III, Brian W. Thompto | 2019-01-29 |
| 10175987 | Instruction prefetching in a computer processor using a prefetch prediction vector | Sheldon B. Levenstein, David S. Levitan, Mauricio J. Serrano | 2019-01-08 |