Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2019-12-03 |
| 10467008 | Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor | David S. Levitan, Mehul Patel, Phillip G. Williams | 2019-11-05 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2019-09-10 |
| 10387154 | Thread migration using a microcode engine of a multi-slice processor | James Wilson Bishop, Marcy E. Byers, Steven R. Carlough, Paul M. Kennedy, Phillip G. Williams | 2019-08-20 |
| 10387686 | Hardware based isolation for secure execution of virtual machines | Richard H. Boivie, Bradly G. Frey, William E. Hall, Benjamin Herrenschmidt, Guerney D. H. Hunt +3 more | 2019-08-20 |
| 10379867 | Asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle +2 more | 2019-08-13 |
| 10353710 | Techniques for predicting a target address of an indirect branch instruction | Richard J. Eickemeyer, Naga P. Gorti, David S. Levitan | 2019-07-16 |
| 10248555 | Managing an effective address table in a multi-slice processor | Akash V. Giri, David S. Levitan, Mehul Patel | 2019-04-02 |
| 10241905 | Managing an effective address table in a multi-slice processor | Akash V. Giri, David S. Levitan, Mehul Patel | 2019-03-26 |
| 10169046 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto +1 more | 2019-01-01 |