Issued Patents 2019
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10516833 | Virtual linebuffers for image signal processors | Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein, Albert Meixner | 2019-12-24 |
| 10489878 | Configurable and programmable image processor unit | Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more | 2019-11-26 |
| 10417732 | Architecture for high performance, power efficient, programmable image processing | Qiuling Zhu, Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, David Patterson +4 more | 2019-09-17 |
| 10397450 | Two dimensional shift array for image processor | Jason Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2019-08-27 |
| 10387988 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Albert Meixner, Hyunchul Park, William R. Mark, Daniel Frederic Finchelstein | 2019-08-20 |
| 10387989 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Albert Meixner, Hyunchul Park, William R. Mark, Daniel Frederic Finchelstein | 2019-08-20 |
| 10334194 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave | 2019-06-25 |
| 10321077 | Line buffer unit for image processor | Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein | 2019-06-11 |
| 10291813 | Sheet generator for image processor | Albert Meixner, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein | 2019-05-14 |
| 10284744 | Sheet generator for image processor | Albert Meixner, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein | 2019-05-07 |
| 10277833 | Virtual linebuffers for image signal processors | Qiuling Zhu, Jason Redgrave, Daniel Frederic Finchelstein, Albert Meixner | 2019-04-30 |
| 10275253 | Energy efficient processor core architecture for image processor | Albert Meixner, Jason Redgrave, Daniel Frederic Finchelstein, Qiuling Zhu | 2019-04-30 |
| 10216487 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Albert Meixner, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Redgrave | 2019-02-26 |
| 10185560 | Multi-functional execution lane for image processor | Artem Vasilyev, Jason Redgrave, Albert Meixner | 2019-01-22 |