| 10516833 |
Virtual linebuffers for image signal processors |
Qiuling Zhu, Ofer Shacham, Jason Redgrave, Daniel Frederic Finchelstein |
2019-12-24 |
| 10504480 |
Macro I/O unit for image processor |
Neeti Desai, Dilan Manatunga, Jason Redgrave, William R. Mark |
2019-12-10 |
| 10489878 |
Configurable and programmable image processor unit |
Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more |
2019-11-26 |
| 10489199 |
Program code transformations to improve image processor runtime efficiency |
Hyunchul Park |
2019-11-26 |
| 10481870 |
Circuit to perform dual input value absolute value and sum operation |
Artem Vasilyev, Jason Redgrave |
2019-11-19 |
| 10467056 |
Configuration of application software on multi-core image processor |
Hyunchul Park |
2019-11-05 |
| 10430919 |
Determination of per line buffer unit memory allocation |
Hyunchul Park, Qiuling Zhu, William R. Mark |
2019-10-01 |
| 10417732 |
Architecture for high performance, power efficient, programmable image processing |
Qiuling Zhu, Ofer Shacham, Jason Redgrave, Daniel Frederic Finchelstein, David Patterson +4 more |
2019-09-17 |
| 10397450 |
Two dimensional shift array for image processor |
Ofer Shacham, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more |
2019-08-27 |
| 10387988 |
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform |
Hyunchul Park, William R. Mark, Daniel Frederic Finchelstein, Ofer Shacham |
2019-08-20 |
| 10387989 |
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform |
Hyunchul Park, William R. Mark, Daniel Frederic Finchelstein, Ofer Shacham |
2019-08-20 |
| 10380969 |
Macro I/O unit for image processor |
Neeti Desai, Dilan Manatunga, Jason Redgrave, William R. Mark |
2019-08-13 |
| 10334194 |
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register |
Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave, Ofer Shacham |
2019-06-25 |
| 10321077 |
Line buffer unit for image processor |
Neeti Desai, Qiuling Zhu, Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein |
2019-06-11 |
| 10304156 |
Compiler managed memory for image processor |
Hyunchul Park, Qiuling Zhu, Jason Redgrave |
2019-05-28 |
| 10291813 |
Sheet generator for image processor |
Jason Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein |
2019-05-14 |
| 10284744 |
Sheet generator for image processor |
Jason Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein |
2019-05-07 |
| 10277833 |
Virtual linebuffers for image signal processors |
Qiuling Zhu, Ofer Shacham, Jason Redgrave, Daniel Frederic Finchelstein |
2019-04-30 |
| 10275253 |
Energy efficient processor core architecture for image processor |
Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu |
2019-04-30 |
| 10216487 |
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure |
Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Redgrave |
2019-02-26 |
| 10204396 |
Compiler managed memory for image processor |
Hyunchul Park, Qiuling Zhu, Jason Redgrave |
2019-02-12 |
| 10185560 |
Multi-functional execution lane for image processor |
Artem Vasilyev, Jason Redgrave, Ofer Shacham |
2019-01-22 |
