| 10516833 |
Virtual linebuffers for image signal processors |
Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein, Albert Meixner |
2019-12-24 |
| 10504480 |
Macro I/O unit for image processor |
Albert Meixner, Neeti Desai, Dilan Manatunga, William R. Mark |
2019-12-10 |
| 10503689 |
Image processor I/O unit |
Asif Khan, Neeti Desai, David N. Warren |
2019-12-10 |
| 10489878 |
Configurable and programmable image processor unit |
Fabrizio Basso, Edward Chang, Daniel Frederic Finchelstein, Timothy O. Knight, William R. Mark +6 more |
2019-11-26 |
| 10481870 |
Circuit to perform dual input value absolute value and sum operation |
Artem Vasilyev, Albert Meixner |
2019-11-19 |
| 10477164 |
Shift register with reduced wiring complexity |
— |
2019-11-12 |
| 10417732 |
Architecture for high performance, power efficient, programmable image processing |
Qiuling Zhu, Ofer Shacham, Albert Meixner, Daniel Frederic Finchelstein, David Patterson +4 more |
2019-09-17 |
| 10397450 |
Two dimensional shift array for image processor |
Ofer Shacham, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more |
2019-08-27 |
| 10380969 |
Macro I/O unit for image processor |
Albert Meixner, Neeti Desai, Dilan Manatunga, William R. Mark |
2019-08-13 |
| 10334194 |
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register |
Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Ofer Shacham |
2019-06-25 |
| 10321077 |
Line buffer unit for image processor |
Neeti Desai, Albert Meixner, Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein |
2019-06-11 |
| 10313641 |
Shift register with reduced wiring complexity |
— |
2019-06-04 |
| 10304156 |
Compiler managed memory for image processor |
Albert Meixner, Hyunchul Park, Qiuling Zhu |
2019-05-28 |
| 10291813 |
Sheet generator for image processor |
Albert Meixner, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein |
2019-05-14 |
| 10284744 |
Sheet generator for image processor |
Albert Meixner, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein |
2019-05-07 |
| 10275253 |
Energy efficient processor core architecture for image processor |
Albert Meixner, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu |
2019-04-30 |
| 10277833 |
Virtual linebuffers for image signal processors |
Qiuling Zhu, Ofer Shacham, Daniel Frederic Finchelstein, Albert Meixner |
2019-04-30 |
| 10242426 |
Multistage collector for outputs in multiprocessor systems |
James Alexander McCombe, Steven J. Clohset, Luke T. Peterson |
2019-03-26 |
| 10216487 |
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure |
Albert Meixner, Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu |
2019-02-26 |
| 10204396 |
Compiler managed memory for image processor |
Albert Meixner, Hyunchul Park, Qiuling Zhu |
2019-02-12 |
| 10185560 |
Multi-functional execution lane for image processor |
Artem Vasilyev, Albert Meixner, Ofer Shacham |
2019-01-22 |
