| 10503509 |
System and method for communication using a register management array circuit |
Alexander Gendler, Michael Mishaeli |
2019-12-10 |
| 10503550 |
Dynamic performance biasing in a processor |
Monica Gupta, Russell J. Fenger, Vijay Dhanraj, Deepak Samuel Kirubakaran, Srividya Ambale +2 more |
2019-12-10 |
| 10503517 |
Method for booting a heterogeneous system and presenting a symmetric core view |
Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt +19 more |
2019-12-10 |
| 10474218 |
Dynamically controlling cache size to maximize energy efficiency |
Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more |
2019-11-12 |
| 10474216 |
Method and apparatus for providing power state information using in-band signaling |
Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim Rotem +3 more |
2019-11-12 |
| 10467012 |
Apparatus and method for accelerating operations in a processor which uses shared virtual memory |
Karthikeyan Vaithianathan, Yoav Zach, Boris Ginzburg, Ronny Ronen |
2019-11-05 |
| 10429919 |
System, apparatus and method for loose lock-step redundancy power management |
Efraim Rotem, Doron Rajwan, Nir Rosenzweig, Yoni Aizik |
2019-10-01 |
| 10379904 |
Controlling a performance state of a processor using a combination of package and thread hint information |
Israel Hirsh, Efraim Rotem, Doron Rajwan, Avinash N. Ananthakrishnan, Natanel Abitan +2 more |
2019-08-13 |
| 10379596 |
Providing an interface for demotion control information in a processor |
Nir Rosenzweig, Efraim Rotem, Yoav Ben-Raphael, Alon Naveh |
2019-08-13 |
| 10372197 |
User level control of power management policies |
Krishnakanth V. Sistla, Jeremy J. Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh +7 more |
2019-08-06 |
| 10372198 |
Controlling performance states of processing engines of a processor |
Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig +3 more |
2019-08-06 |
| 10346195 |
Apparatus and method for invocation of a multi threaded accelerator |
Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Yuval Yosef |
2019-07-09 |
| 10345889 |
Forcing a processor into a low power state |
Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper +11 more |
2019-07-09 |
| 10324519 |
Controlling forced idle state operation in a processor |
Efraim Rotem, Yoni Aizik, Doron Rajwan, Gal Leibovich, Nadav Shulman +1 more |
2019-06-18 |
| 10281975 |
Processor having accelerated user responsiveness in constrained environment |
Efraim Rotem, Doron Rajwan, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos +1 more |
2019-05-07 |
| 10275260 |
Collaborative processor and system performance and power management |
Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall +2 more |
2019-04-30 |
| 10248181 |
Enabling a non-core domain to control memory bandwidth in a processor |
Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Ryan D. Wells |
2019-04-02 |
| 10216246 |
Multi-level loops for computer processor control |
Doron Rajwan, Efraim Rotem, Avinash N. Ananthakrishnan, Dorit Shapira |
2019-02-26 |
| 10191742 |
Mechanism for saving and retrieving micro-architecture context |
Efraim Rotem, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen |
2019-01-29 |
| 10185566 |
Migrating tasks between asymmetric computing elements of a multi-core processor |
Alon Naveh, Yuval Yosef, Anil Aggarwal, Efraim Rotem, Avi Mendelson +7 more |
2019-01-22 |
| 10175740 |
Mapping a performance request to an operating frequency in a processor |
Efraim Rotem, Paul S. Diefenbaugh, Guy M. Therien, Nir Rosenzweig |
2019-01-08 |